1. Field of the Invention
The present invention relates to a memory.
2. Description of the Background Art
In general, volatile and nonvolatile memories are known as semiconductor memories. A DRAM (dynamic random access memory) is known as the nonvolatile memory, and a flash EEPROM (electrically erasable and programmable read only memory) is known as the nonvolatile memory. The DRAM and the flash EEPROM, which can be highly integrated, are widely employed.
FIG. 58 is an equivalent circuit diagram showing the structure of a memory cell 103 of a conventional DRAM. FIG. 59 is a sectional view showing the structure of a trench-type capacitor 102 employed for the conventional DRAM. Referring to FIG. 58, the memory cell 103 of the conventional DRAM serving as a nonvolatile memory is formed by a selection transistor 101 and the capacitor 102. The capacitor 102 stores information of the memory cell 103 as charges. In order to read information from the memory cell 103, a word line WL rises to bring the selection transistor 101 into an ON state. Thus, a cell capacitance Ccell and a bit line capacitance Cb1 are capacitively coupled with each other. Therefore, a bit line potential depending on the quantity of the charges stored in the memory cell 103 can be read.
In the memory cell 103 of the conventional DRAM having the aforementioned structure, an upper electrode 102a, a lower electrode 102c and a dielectric film 102b forming the trench-type capacitor 102 are longitudinally extended as shown in FIG. 59, in order to ensure the cell capacitance Ccell of the capacitor 102 also when the same is refined. If refinement further progresses, however, it is difficult to ensure the capacitance of the capacitor 102 also when employing the trench structure shown in FIG. 59. In other words, high integration of the DRAM resulting from reduction of a design rule approaches to the limit.
In the flash EEPROM (hereinafter referred to as a flash memory) serving as the nonvolatile memory, a memory cell of a CHE (channel hot electron) system such as a stacked or split gate memory cell is limited in refinement of the channel length. In a memory cell of an FN (Fouler-Nordheim) write system such as a NAND memory cell, the limit of refinement is equivalent to that of a logic transistor. However, the flash memory requires a high voltage of 15 V to 20 V for operations, and if the power supply voltage for the logic transistor is reduced, efficiency for forming the high voltage of 15 V to 20 V from the low power supply voltage is reduced. Therefore, power consumption is increased and the area of a charge pumping part is also increased, to disadvantageously hinder refinement.
A ferroelectric memory is known as one of recently noted nonvolatile memories. The ferroelectric memory utilizes pseudo capacitance change resulting from the direction of polarization of a ferroelectric substance as a memory element. The ferroelectric memory, capable of rewriting data at a high speed with a low voltage in principle, is spotlighted as an ideal memory having the advantages of the high speed and the low voltage of the DRAM as well as the advantage of nonvolatility of the flash memory.
Memory cell systems for a ferroelectric memory are roughly classified into three types of systems, i.e., a one-transistor one-capacitor system, a simple matrix system and a one-transistor system. FIG. 60 is an equivalent circuit diagram showing a memory cell 113 of a one-transistor one-capacitor ferroelectric memory. FIG. 61 is an equivalent circuit diagram showing a memory cell array of a simple matrix ferroelectric memory. FIG. 62 is a hysteresis diagram for illustrating operations of the simple matrix ferroelectric memory, and FIG. 63 is a hysteresis diagram for illustrating disturbance in the simple matrix ferroelectric memory. FIG. 64 is an equivalent circuit diagram showing a memory cell 131 of a one-transistor ferroelectric memory, and FIG. 65 is a hysteresis diagram for illustrating operations of the one-transistor ferroelectric memory. FIG. 66 is an equivalent circuit diagram for illustrating a voltage application state in writing of the one-transistor ferroelectric memory shown in FIG. 64, and FIG. 67 is an equivalent circuit diagram for illustrating a voltage application state in a standby state of the one-transistor ferroelectric memory shown in FIG. 64.
As shown in FIG. 60, the memory cell 113 of the one-transistor one-capacitor ferroelectric memory is formed bya selection transistor 111 and a ferroelectric capacitor 112, similarly to that of the DRAM. The memory cell 113 is different from that of the DRAM in the ferroelectric capacitor 112. In operation, a word line WL rises for bringing the selection transistor 111 into an ON state. Thus, a capacitor capacitance Ccell of the ferroelectric capacitor 112 is connected with a bit line capacitance Cb1. Then, a plate line PL is pulse-driven for transmitting charges in a quantity varying with the direction of polarization of the ferroelectric capacitor 112. The ferroelectric memory reads data as the voltage of the bit line BL, similarly to the case of the DRAM.
In the one-transistor one-capacitor ferroelectric memory having a structure similar to that of the DRAM, refinement of the ferroelectric capacitor 112 is limited. Therefore, the ferroelectric memory is limited in high integration similarly to the DRAM.
The simple matrix ferroelectric memory is now described with reference to FIGS. 61 to 63. As shown in FIG. 61, each memory cell 121 of the simple matrix ferroelectric memory is constituted by a ferroelectric capacitor 122 consisting of a word line WL and a bit line BL formed to extend in directions intersecting with each other and a ferroelectric film (not shown) arranged between the word line WL and the bit line WL. An end of the ferroelectric capacitor 122 is connected to the word line WL while another end thereof is connected to the bit line BL. The simple matrix ferroelectric memory, reading a potential resulting from capacitive coupling between the bit line BL and the ferroelectric capacitor 122, must ensure capacitances similarly to the DRAM. In the simple matrix ferroelectric memory, however, each memory cell 121 is formed by only the ferroelectric capacitor 122 with no selection transistor, whereby the degree of integration can be improved as compared with the one-transistor one-capacitor ferroelectric memory.
Operations of the simple matrix ferroelectric memory are now described with reference to FIGS. 61 and 62. Table 1 shows voltages applied to each cell 121 in reading/writing.
In a write operation, both ends of the ferroelectric capacitor 122 are at the same potential in a standby state. In order to write data xe2x80x9c0xe2x80x9d, the simple matrix ferroelectric memory applies a voltage Vcc to the word line WL while applying a voltage of 0 V to the bit line BL. At this time, the simple matrix ferroelectric memory applies the voltage Vcc to the ferroelectric capacitor 122, thereby making a transition to a point A shown in FIG. 62. Thereafter the simple matrix ferroelectric memory sets both ends of the ferroelectric capacitor 122 to the same potential, for making a transition to xe2x80x9c0xe2x80x9d shown in FIG. 62. In order to write data xe2x80x9c1xe2x80x9d, the simple matrix ferroelectric memory applies the voltage 0 V to the word line WL while applying the voltage Vcc to the bit line BL. At this time, the simple matrix ferroelectric memory applies a voltage xe2x88x92Vcc to the ferroelectric capacitor 122, thereby making a transition to a point B in FIG. 62. Thereafter the simple matrix ferroelectric memory sets both ends of the ferroelectric capacitor 122 to the same potential, for making a transition to xe2x80x9c1xe2x80x9d shown in FIG. 62.
In a read operation, the simple matrix ferroelectric memory first precharges the bit line BL to 0 V. Then, the simple matrix ferroelectric memory raises the word line WL to the voltage Vcc. This voltage is Vcc capacitively divided by a capacitance CFE of the ferroelectric capacitor 122 and a parasitic capacitance CBL of the bit line BL. The capacitance CFE of the ferroelectric capacitor 122 can be approximated as a capacitance C0 or C1 depending on held data. Therefore, the potential of the bit line BL is expressed as follows:
V0={C0/(C0+CBL)}xc3x97Vccxe2x80x83xe2x80x83(1)
V1={C1/(C1+CBL)}xc3x97Vccxe2x80x83xe2x80x83(2)
The equation (1) expresses the potential V0 of the bit line BL when holding data xe2x80x9c0xe2x80x9d, and the equation (2) expresses the potential V1 of the bit line BL when holding data xe2x80x9c1xe2x80x9d.
The simple matrix ferroelectric memory determines the potential difference between the bit line potentials V0 and V1 expressed in the above equations (1) and (2) respectively with a read amplifier, thereby reading the data. Data of the memory cell 121 is destroyed in this data reading and hence the simple matrix ferroelectric memory performs a write operation (restore operation) responsive to read data after the data reading.
In the simple matrix ferroelectric memory, however, data of non-selected cells disadvantageously disappear due to disturbance. In other words, it follows that a voltage ⅓Vcc is applied to all non-selected memory cells in writing and reading. As shown in FIG. 63, therefore, the quantity of polarization is decreased due to hysteresis characteristics of a ferroelectric substance, to result in disappearance of data.
The one-transistor ferroelectric memory is now described with reference to FIGS. 64 to 67. As shown in FIG. 64, the memory cell 131 of the one-transistor ferroelectric memory is formed by connecting a ferroelectric capacitor 132 to the gate of a MOS transistor 133. In the one-transistor ferroelectric memory, an end of the ferroelectric capacitor 132 is connected to a word line WL, while the other end thereof is connected to the gate of the MOS transistor 133 forming a cell transistor. In the one-transistor ferroelectric memory, the threshold voltage of the MOS transistor 133 varies with the direction of polarization of the ferroelectric capacitor 132, to change a memory cell current. The one-transistor ferroelectric memory reads data by determining this change of the memory cell current. The one-transistor ferroelectric memory reads data by detecting the memory cell current, and hence the capacitance of the ferroelectric capacitor 132 may not be increased to some extent in consideration of the bit line capacitance, dissimilarly to the one-transistor one-capacitor ferroelectric memory shown in FIG. 60. Therefore, the ferroelectric capacitor 132 can be reduced in size so that the one-transistor ferroelectric memory is suitable for refinement.
Operations of the one-transistor ferroelectric memory are now described. In a standby state, every word line WL, every bit line BL and every source line SL are at 0 V. In a write operation, the one-transistor ferroelectric memory applies a step-up voltage Vpp to the word line WL, in order to write data xe2x80x9c0xe2x80x9d. At this time, the one-transistor ferroelectric memory applies a potential capacitively divided with the gate capacitance of the MOS transistor 133 to the ferroelectric capacitor 132, thereby making a transition to a point A shown in FIG. 65 despite an initial state. Thereafter the one-transistor ferroelectric memory returns the word line WL to 0 V, for making a transition to data xe2x80x9c0xe2x80x9d shown in FIG. 65. In order to write data xe2x80x9c1xe2x80x9d, the one-transistor ferroelectric memory applies a voltage of 0 V to the word line WL while applying the step-up voltage Vpp to the bit line BL. In this case, the one-transistor ferroelectric memory applies a voltage xe2x88x92Vcc to the ferroelectric capacitor 132, thereby making a transition to a point B shown in FIG. 65. Thereafter the one-transistor ferroelectric memory returns the bit line BL to 0 V, thereby making a transition to data xe2x80x9c1xe2x80x9d shown in FIG. 65.
In a read operation, the one-transistor ferroelectric memory raises the word line WL to a voltage Vr causing no polarization inversion. Thus, the gate voltage of the cell transistor (MOS transistor) 133 varies with a write state. A current flowing through the cell transistor 133 varies with change of the gate voltage of the cell transistor 133, and the one-transistor ferroelectric memory reads the current difference through the bit line BL. The one-transistor ferroelectric memory, which may read not potential difference resulting from capacitive coupling between the ferroelectric capacitor 132 and a bit-line capacitance but the current of the cell transistor 133, requires no polarization inversion in reading. Therefore, the one-transistor ferroelectric memory is capable of non-destructive reading.
However, the one-transistor ferroelectric memory also has the problem of disturbance of non-selected cells, similarly to the aforementioned simple matrix ferroelectric memory. Further, data changes by the so-called reverse bias retention resulting from a continuous reverse bias state to the ferroelectric capacitor 132. When the one-transistor ferroelectric memory applies the step-up voltage Vpp to the word line WL thereby writing data as shown in FIG. 66 and thereafter returns to the standby state in data writing, a potential opposite to polarization is continuously applied as shown in FIG. 67. Therefore, the data holding time is disadvantageously reduced.
As hereinabove described, it is difficult to refine the conventional DRAM and the conventional flash memory, and hence a memory cell system allowing a higher degree of integration is demanded. While the one-transistor ferroelectric memory and the simple matrix ferroelectric memory can be high integrated, data of non-selected cells disappear due to disturbance or data change by reverse bias retention resulting from a continuous reverse bias state, as hereinabove described. Thus, it is difficult to put the conventional one-transistor and simple matrix ferroelectric memories into practice.
An object of the present invention is to provide a memory capable of suppressing disturbance erasing data from non-selected cells.
In order to attain the aforementioned object, a memory according to an aspect of the present invention comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, for applying a first voltage pulse providing an electric field of a first direction and a second voltage pulse providing an electric field opposite to the first direction to the first storage means by the same number of times respectively throughout a read operation and an operation of rewriting read data while varying a technique for applying the first voltage pulse and the second voltage pulse to the first storage means with a case of reading first data by the read operation and with a case of reading second data by the read operation.
The memory according to the aforementioned aspect applies the first voltage pulse and the second voltage pulse of opposite directions to non-selected first storage means by the same number of times throughout the read operation and the operation of rewriting the read data as hereinabove described thereby canceling polarization deterioration resulting from disturbance in the first storage means of a non-selected cell for inhibiting the non-selected cell from disturbance. Further, the memory varies the technique for applying the first voltage pulse and the second voltage pulse to the first storage means with the case of reading the first data by the read operation and with the case of reading the second data by the read operation, to be capable of applying voltages of opposite directions to the non-selected first storage means by the same number of necessary times in the case of reading the first data and the case of reading the second data independently of each other.
The memory according to the aforementioned aspect preferably applies the first voltage pulse and the second voltage pulse of opposite directions once or substantially applies no voltages when reading the first data by the read operation, while applying the first voltage pulse and the second voltage pulse of opposite directions twice or substantially applying no voltages when reading the second data by the read operation. According to this structure, polarization deterioration is easily canceled in the non-selected first storage means when the memory reads the first data and the second data, whereby the non-selected first storage means can be inhibited from disturbance. The memory may apply voltage pulses having absolutely identical or different forms as the voltage pulses applied twice.
The memory according to the aforementioned aspect preferably performs the read operation and a rewrite operation of the first data when reading the first data by the read operation, while performing the read operation, the rewrite operation of the first data, a compensatory operation for rewriting the second data and a rewrite operation of the second data when reading the second data by the read operation. According to this structure, the memory can easily apply voltage pulses of opposite directions to the non-selected first storage means by the same number of necessary times in the case of reading the first data and the case of reading the second data independently of each other.
In the memory according to the aforementioned aspect, the operation of varying the technique for applying the first voltage pulse and the second voltage pulse to the first storage means may include an operation of varying the procedure for applying the first voltage pulse and the second voltage pulse to the first storage means. The wording xe2x80x9cvarying the procedure for applying the first voltage pulse and the second voltage pulsexe2x80x9d indicates an operation of varying the sequence of application, i.e., varying the number and directions of the voltage pulses. Further, the first storage means receiving the first voltage pulse and the second voltage pulse may include selected first storage means connected to a selected bit line and a selected word line and non-selected first storage means other than the selected first storage means.
The memory according to the aforementioned aspect preferably performs the read operation, two operations of writing the first data and an operation of rewriting the second data when reading the second data by the read operation. According to this structure, polarization deterioration resulting from disturbance is easily canceled in the non-selected first storage means when the memory reads the second data by the read operation, whereby the non-selected first storage means can be inhibited from disturbance. Further, the memory requires no separate circuit for generating a compensatory operation.
The memory according to the aforementioned aspect may start the read operation after setting the word line and the bit line to substantially identical potentials.
The memory according to the aforementioned aspect preferably applies a voltage substantially ⅓ of a voltage applied to the selected first storage means to the non-selected first storage means. According to this structure, difference between the voltages applied to the selected and non-selected first storage means can be maximized, whereby the non-selected first storage means can be further inhibited from disturbance. The wording xe2x80x9cvoltage substantially ⅓ of the voltage applied to the first storage meansxe2x80x9d indicates a voltage value included within the range of at least ⅓Vinxc3x970.9 and not more than ⅓Vinxc3x971.1 assuming that Vin represents the voltage applied to the first storage means.
The memory according to the aforementioned aspect may apply a voltage substantially ⅓ of a voltage applied to selected first storage means when rewriting the data to non-selected first storage means connected to a non-selected bit line while applying a voltage smaller than substantially ⅓ of the voltage applied to the selected first storage means when rewriting the data to the non-selected first storage means connected to a selected bit line in the read operation. The memory according to the aforementioned aspect may apply a voltage smaller than substantially ⅓ of a voltage applied to selected first storage means when rewriting the data to non-selected first storage means connected to a selected bit line and thereafter apply a voltage substantially ⅓ of the voltage applied to the selected first storage means when rewriting the data in the read operation. The wording xe2x80x9cvoltage smaller than substantially ⅓ of the voltage applied to the selected first storage means when rewriting dataxe2x80x9d indicates a positive or negative voltage having an absolute value smaller than the absolute value of a voltage substantially ⅓ of the voltage applied to the selected first storage means when rewriting data.
The memory according to the aforementioned aspect may apply a voltage substantially xc2xd of a voltage applied to selected first storage means or no voltage to non-selected first storage means. The wording xe2x80x9cvoltage substantially xc2xd of the voltage applied to the selected first storage meansxe2x80x9d indicates a voltage value included within the range of at least xc2xdVinxc3x970.9 and not more than xc2xdVinxc3x971.1 assuming that Vin represents the voltage applied to the selected first storage means. The memory according to the aforementioned aspect may apply a voltage substantially xc2xd of a voltage applied to selected first storage means when rewriting the data or no voltage to non-selected first storage means connected to a non-selected bit line while applying a voltage smaller than substantially xc2xd of the voltage applied to the selected first storage means when rewriting the data or no voltage to the non-selected first storage means connected to a selected bit line in the read operation. The wording xe2x80x9cvoltage smaller than substantially xc2xd of the voltage applied to the selected first storage means when rewriting dataxe2x80x9d indicates a positive or negative voltage having an absolute value smaller than the absolute value of a voltage substantially xc2xd of the voltage applied to the selected first storage means when rewriting data.
The memory according to the aforementioned aspect may apply a voltage smaller than substantially xc2xd of a voltage applied to selected first storage means when rewriting the data to non-selected first storage means connected to a selected bit line and thereafter apply a voltage substantially xc2xd of the voltage applied to the selected first storage means when rewriting the data in the read operation, or may substantially apply no voltage to the non-selected first storage means connected to the non-selected bit line throughout the read operation.
The memory according to the aforementioned aspect preferably performs the read operation by sensing the voltage of a selected bit line. According to this structure, the voltage of the selected bit line varies with the case of reading the first data and with the case of reading the second data, whereby the memory can easily read data. In this case, the memory preferably senses the voltage of the selected bit line in a first period and thereafter returns the voltage of the selected bit line substantially to 0 V. in a second period in the read operation, while the first period is preferably set to such a length that change of the quantity of polarization applied to non-selected first storage means connected to the selected bit line in the first period is sufficiently reduced as compared with change of the quantity of polarization applied to the non-selected first storage means connected to the selected bit line in the second period, and the second period is preferably set to such a length that the non-selected first storage means connected to the selected bit line receives change equivalent to change of the quantity of polarization applied to the non-selected first storage means connected to the selected bit line in the rewrite operation. According to this structure, polarization deterioration and polarization improvement are alternately repeated by the same number of times also in the non-selected first storage means connected to the selected bit line, whereby the non-selected first storage means connected to the selected bit line can be also inhibited from disturbance.
The memory according to the aforementioned aspect preferably performs the read operation by sensing a current flowing through a selected word line. According to this structure, the current flowing through the selected word line varies with the case of reading the first data and with the case of reading the second data, whereby the memory can readily read the data.
The memory according to the aforementioned aspect preferably performs the read operation by comparing the value of a current flowing through a selected word line with the value of a current flowing through a selected bit line. According to this structure, the value of the current flowing through the selected word line is identical to that of the current flowing through the selected bit line when the memory reads the first data while the value of the current flowing through the selected word line is different from the value of the current flowing through the selected bit line when the memory reads the second data, whereby the memory can easily read the data.
The memory according to the aforementioned aspect preferably further comprises a dummy cell including second storage means outputting reference data to be compared with data read by the read operation, for applying the first voltage pulse providing the electric field of the first direction and the second voltage pulse providing the electric field opposite to the first direction by the same number of times or substantially applying no voltage to the second storage means also in the dummy cell. According to this structure, non-selected first storage means can be inhibited from disturbance also in the dummy cell, whereby the memory can correctly read data when comparing the data read by the read operation with the reference data.
In this case, a region formed with the memory cell and a region formed with the dummy cell may be divided by dividing the word line, or the region formed with the memory cell and the region formed with the dummy cell may be divided by dividing the bit line.
The memory according to the aforementioned aspect preferably previously writes data reverse to data to be written and thereafter writes the data to be written in a data write operation. According to this structure, polarization deterioration resulting from disturbance is cancelled in non-selected first storage means, whereby the non-selected first storage means can be inhibited from disturbance.
In the memory according to the aforementioned aspect, the memory cell preferably includes a memory cell constituted by a ferroelectric capacitor consisting of the word line and the bit line formed to extend in directions intersecting with each other and a ferroelectric film arranged between the word line and the bit line. According to this structure, non-selected first storage means can be easily inhibited from disturbance in a simple matrix ferroelectric memory.
In the memory according to the aforementioned aspect, the memory cell preferably includes a memory cell constituted by a ferroelectric capacitor and a load capacitance. According to this structure, non-selected first storage means can be easily inhibited from disturbance in a simple matrix ferroelectric memory including the memory cell constituted by a ferroelectric capacitor and a load capacitance. In this case, the load capacitance may be either a ferroelectric capacitor or a paraelectric capacitor. Further, the memory applies a voltage substantially (Cf+Ce)/Ce times a voltage applied when the memory cell is constituted by only the ferroelectric capacitor to the memory cell assuming that Cf represents the capacitance of the ferroelectric capacitor and Ce represents the load capacitance. According to this structure, voltage arrangement according to the present invention can be easily applied to a ferroelectric memory including the memory cell constituted by a ferroelectric capacitor and a load capacitance.
In the memory according to the aforementioned aspect, the memory cell preferably includes a memory cell having a ferroelectric capacitor including an end connected to the word line and another end connected to a gate electrode of a transistor. According to this structure, non-selected first storage means can be easily inhibited from disturbance in an FET-type ferroelectric memory. In this case, the memory performs the read operation of the data by measuring the drain current of the transistor. According to this structure, the value of the drain current varies with the case of reading the first data and with the case of reading the second data, whereby the memory can easily read the data. Further, the memory applies a voltage substantially (Cf+Cg)/Cg times a voltage applied when the memory cell is constituted by only the ferroelectric capacitor to the memory cell assuming that Cf represents the capacitance of the ferroelectric capacitor and Cg represents the capacitance of the gate electrode. According to this structure, the voltage arrangement of the present invention can be easily applied to the FET-type ferroelectric memory.
The memory according to the aforementioned aspect preferably has a first structure of applying the first voltage pulse and the second voltage pulse of opposite directions having the same values to at least non-selected first storage means not sharing the word line and the bit line with selected first storage means and non-selected first storage means sharing the word line with the selected first storage means among non-selected first storage means or substantially applying no voltage throughout the read operation and the operation of rewriting the read data. According to this structure, at least the first storage means not sharing the word line and the bit line with the selected first storage means and the first storage means sharing the word line with the selected first storage means can be inhibited from disturbance among the non-selected first storage means.
In the memory according to the aforementioned aspect, the first voltage pulse and the second voltage pulse of opposite directions having the same values are preferably substantially ⅓ of a voltage applied to the first storage means when writing data, and the memory preferably applies the first voltage pulse and the second voltage pulse of opposite directions substantially ⅓ of the voltage applied to the first storage means when writing the data to at least the non-selected fist storage means not sharing the word line and the bit line with the selected first storage means and the non-selected first storage means sharing the word line with the selected first storage means among the non-selected first storage means throughout the read operation and the operation of rewriting the read data. According to this structure, at least the first storage means not sharing the word line and the bit line with the selected first storage means and the first storage means sharing the word line with the selected first storage means can be inhibited from disturbance among the non-selected first storage means when employing a ⅓Vcc method.
In this case, the memory preferably applies the first voltage pulse and the second voltage pulse of opposite directions substantially ⅓ of the voltage applied to the first storage means when writing the data also to non-selected first storage means sharing the bit line with the selected first memory means among the non-selected first storage means by the same number of times throughout the read operation and the operation of rewriting the read data. According to this structure, the first storage means sharing the bit line with the selected first storage means can also be inhibited from disturbance in addition to the first storage means not sharing the word line and the bit line with the selected first storage means and the first storage means sharing the word line with the selected first storage means, whereby all non-selected first storage means can be inhibited from disturbance.
In the memory according to the aforementioned aspect, the first voltage pulse and the second voltage pulse of opposite directions having the same values are preferably substantially xc2xd of a voltage applied to the first storage means when writing data, and the memory preferably applies the first voltage pulse and the second voltage pulse of opposite directions substantially xc2xd of the voltage applied to the first storage means when writing the data to at least the non-selected first storage means sharing the word line with the selected first storage means by the same number of times while substantially applying no voltage to the non-selected first storage means not sharing the word line and said bit line with the selected first storage means throughout the read operation and the operation of rewriting the read data. According to this structure, at least the first storage means not sharing the word line and the bit line with the selected first storage means and the first storage means sharing the word line with the selected first storage means can be inhibited from disturbance among the non-selected first storage means when employing a xc2xdVcc method.
The memory according to the aforementioned aspect may apply a prescribed voltage to selected first storage means while applying a voltage m/n (m, n: positive integers) of the prescribed voltage to non-selected first storage means in the read operation and the rewrite operation. In this case, the memory preferably applies a voltage ⅓ of the prescribed voltage to the non-selected first storage means. According to this structure, the difference between the voltages applied to the selected first storage means and the non-selected first storage means can be maximized, whereby the non-selected first storage means can be further prevented from disturbance.
In the memory according to the aforementioned aspect, the first storage means may include a ferroelectric film, or may include a resistive element.
The memory according to the aforementioned aspect may apply a voltage not more than a polarization-inverted coercive voltage to non-selected first storage means. According to this structure, the quantity of deterioration finally caused in the non-selected cells can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.